This invention relates to a phase-locked loop circuit and, more particularly, to a phase-locked loop circuit of fractional frequency-dividing type.
In order to control the frequency of an output signal at a frequency interval smaller than the frequency of a reference signal, the conventional practice is to employ an arrangement which averages, in terms of time, a frequency dividing ratio of a programmable frequency dividing circuit with the frequency dividing ratio being variable in an ordinary phase-locked loop (PLL) to implement a frequency dividing ratio of an accuracy finer than a decimal-point by using the average value. A configuration in which the dividing ratio of a frequency dividing circuit is changed and averaged in terms of time to implement fractional frequency division in equivalent terms is also referred to as a fractional frequency-dividing system.
If one period 1/fr of a reference signal of which frequency is fr is adopted as one clock, then, by switching the frequency dividing ratio from M to M+1 only once over L clocks (time T), the average value of the dividing ratio over the time T will be given by M+1/L.
By extending the term 1/L of this fractional part to k/L, where k=0, 1, 2, . . . , the frequency dividing ratio can be set at steps of 1/L. The frequency-dividing ratio is given as follows.
Mave=M+k/L(0= less than k= less than L, where k is an integer)
FIG. 15 is a block diagram illustrating the structure and principle of such a fractional frequency-dividing PLL circuit. A phase comparator, a charge pump, a loop filter and a voltage-controlled oscillator of the PLL circuit have been deleted from the diagram of FIG. 15; only a frequency dividing circuit and a control circuit thereof are shown. As illustrated in FIG. 15, the PLL circuit is constituted by an accumulator 600 comprising an adder 602 and a register 603, and a variable frequency dividing circuit 601 for dividing frequency at a dividing ratio M or M+1 (where M is a predetermined integer). The adder 602 performs addition at increments of k in response to a clock whose frequency is equal to a reference frequency. The frequency dividing ratio of the frequency divider becomes M+1 when the adder 602 overflows and is M when the adder 602 does not overflow.
When the dividing ratio is changed periodically, as in the fractional frequency dividing scheme of the arrangement shown in FIG. 15, a spurious having frequency components of a period of this change is generated. In other words, if T represents a period of the change in the frequency dividing ratio of the frequency dividing circuit 601, then in the output of the PLL circuit (the output of the voltage-controlled oscillator) is generated spurious frequency components which are equally spaced by a frequency interval 1/T from the center frequency of the output of the voltage-controlled oscillator.
In order to reduce this spurious component, the specification of Japanese Patent Application Laid-Open No. 8-8741 discloses an arrangement of the kind shown in FIG. 16 as a frequency synthesizer (PLL circuit) for controlling output-signal frequency at frequency intervals that are smaller than a reference-signal frequency, thereby reducing spurious components in the vicinity of the center frequency of the output signal. The arrangement shown in FIG. 16 includes a phase comparator 701, a low-pass filter 702, a voltage-controlled oscillator 703, a variable frequency divider 704, a frequency dividing adder 711, accumulators 706 to 709, and a frequency-division control circuit 705. In accordance with a value set from the frequency-division control circuit 705, the variable frequency divider 704 divides and outputs the frequency of the output signal from voltage-controlled oscillator (VCO) 703. The phase comparator 701 compares a phase of the output of the variable frequency divider 704 and a phase of a reference frequency and outputs a phase difference. The output of the phase comparator 701 is input to the voltage-controlled oscillator 703 via the low-pass filter 702 and control is performed in such a manner that the signal obtained by frequency-dividing the Output signal of the voltage-controlled oscillator 703 will be synchronized to the reference signal. The Output of the voltage-controlled oscillator 703 is delivered as the output signal and is input to the variable frequency divider 704.
The frequency-division control circuit 705 comprises accumulators 706, 707, 708, and 709, a fractional part calculating circuit 710 and the frequency dividing ratio adder 711 Each of these circuits operates with the output of the variable frequency divider 704 serving as the clock. The accumulator 706, which comprises an adder and a register, adds the value of the register to a fractional data, which has been provided externally, synchronizing with the clock, and updates the register. The accumulator 707, which comprises an adder and a register, adds the output value of the accumulator 706 to the value of its register in sync with the clock, thereby adding 1 to the least significant bit, and updates the values value of its register. The accumulators 707 and 708 are identically constructed. The adder of each accumulator outputs the carry signal of its most significant bit and inputs the carry signal to the decimal calculating circuit 710.
The fractional part calculating circuit 710 operates in synchronization with the clock. When the accumulator 706 generates a carry signal, the fractional part calculating circuit 710 generates +1 after three clock pulses. When a carry signal enters from the accumulator 707, the fractional part calculating circuit 710 generates +1 after two clock pulses and +1 after three clock pulses. When a carry signal enters from the accumulator 708, the fractional part calculating circuit 710 generates in turn +1 after one clock pulse; xe2x88x922 after two clocks pulses a +1 after three clock pulses. When a carry signal enters from the accumulator 709, the fractional part calculating circuit 710 generates in turn +1 after 0 clock pulses, xe2x88x923 after one clock pulse, +3 after two clock pulses and xe2x88x921 after three clock pulses.
The total sum of the values generated by the carry signals produced by each of the accumulators at each clock is output to the fractional part calculating circuit 710. The frequency dividing adder 711 adds the decimal output of the fractional part calculating circuit 710 and the value of the integer, and the result becomes the output of the frequency-division control circuit 705, which sets the dividing ratio of the variable frequency divider 704. As a result, a change in the dividing ratio is produced clock by clock, the frequency components of the change in dividing ratio are raised and the low frequency components are lowered. The changes in the dividing ratio brought about by the carry signals from the accumulators 707 to 709 have no influence upon the averaged dividing ratio because the respective averages over time are zero; only the carry produced by the accumulator 706 contributes to the averaged dividing ratio.
If M represents an integer data, K a fraction data and n the number of bits constituting the accumulator 706, the accumulator 706 will generate K carries over 2n clocks and the dividing ratio will be made M+1 K times. The averaged dividing ratio, therefore, will be M+K/2n. If fr represents the frequency of the reference signal, then the output frequency will be frxc2x7(M+K/2n).
Though the frequency component of a change in dividing ratio appears as a spurious Output from the VCO, the frequency of the change in dividing ratio resulting from connecting the accumulators in four stages increases and the low frequency component decreases. The periodic change is disturbed by always adding 1 to the least significant bit of the accumulator 707 and a spurious component is not produced at a frequency offset by frxc2x7K/2n/4 from the center frequency of the output signal. The effect of diminishing the low frequency component, therefore, is not sacrificed.
An arrangement of the kind shown in FIG. 17 (which uses the so-called xe2x80x9cDelta-Sigmaxe2x80x9d technique) also is known as a PLL circuit of the fractional frequency-dividing type. Here a dividing-ratio control circuit 908 for controlling the dividing ratio of a frequency dividing circuit 907 varies and controls a change delta-N in dividing ratio based upon the results of calculations by accumulators operated by a frequency-divided clock. The period of this variation is obtained by a predetermined modulo calculation.
Also known is a PLL circuit having means which compensates for the charge and discharge current of a charge pump resulting from the occurrence of a spurious signal caused by periodically varying a frequency dividing ratio. For example, as shown in FIGS. 18 and 19, charge pumps 831, 832 for charging and discharging a capacitance by up and down signals output from a phase comparator 803 each have a compensating charge pump. Each of the charge pumps has an array of unit charge pumps CP comprising a P-channel MOS transistor turned on by the up signal and an N-channel MOS transistor turned on by the down signal. The sum of the current outputs of the plurality of unit charge pumps CP is extracted as the output. A reference current is varied by a digital-to-analog converter 836 and then applied to the compensating charge pumps, and the compensating current outputs of these charge pumps are turned on and off by the output of a decoder 834, whereby current is varied.
In all of the arrangements described above, fractional frequency division is achieved by changing and then averaging the dividing ratio of a variable frequency divider, and a spurious signal is produced in the output of a voltage-controlled oscillator due to the change in the dividing ratio of the frequency divider. The above-mentioned arrangements are for suppressing and compensating for such spurious signals. In other words, none of these arrangements has a construction that is free of spurious signals.
As a consequence, a problem with the prior art is that the circuitry for reducing spurious signals becomes large in scale. For example, arrangements (FIGS. 18 and 19) for suppressing spurious signals by compensating charge-pump current involve circuitry of very large scale.
Accordingly, it is an object of the present invention to provide an entirely novel PLL circuit that makes fractional frequency division possible without causing spurious signals to be produced in the output of a voltage-controlled oscillator.
The foregoing object is accomplished in accordance with one aspect of the present invention by providing a PLL circuit comprising: a phase comparator circuit which receives a reference clock from one input terminal thereof to output a phase difference; a charge pump which generates a voltage conforming to the phase difference output from said phase comparator circuit; a loop filter which performs smoothing the voltage conforming to the phase difference; a voltage-controlled oscillator which receives an output voltage of said loop filter as a control voltage to output a clock having an oscillation frequency determined by the control voltage; a frequency dividing circuit which performs integral frequency-division of an output clock output from said voltage-controlled oscillator; a phase adjusting circuit which receives two frequency-divided clocks of mutually different phases obtained by integral frequency division at said frequency dividing circuit to produce an output signal having a delay time defined by a time that is the result of dividing a timing difference between the two frequency-divided clocks in accordance with a prescribed interior division ratio, said interior division ratio being made variable; and control means which provides a signal for variably setting, every integral frequency dividing interval, the interior division ratio with which the timing difference is divided in the phase adjusting circuit; wherein a frequency-divided clock that is output from said phase adjusting circuit is fed to another input terminal of said phase comparator circuit so that a phase of the frequency-divided clock is compared with that of the reference clock.
In accordance with another aspect of the present invention, the dividing ratio for frequency dividing the clock output of the voltage-controlled oscillator is N+MF/MD, which is defined by an integral dividing ratio N and a fractional dividing ratio MF/MD. The frequency dividing circuit has its integral dividing ratio set to N or N+1, and the control means has an adder circuit for performing addition cumulatively in units of MF based upon the frequency-divided clock obtained by integral frequency division.
In accordance with another aspect of the present invention, the PLL circuit further includes a control circuit which, if the result of cumulative addition is equal to or greater than MD, adopts a remainder obtained by dividing this result by MD as a new cumulative result, and which if, a value of addition of MF to the present cumulative result, is equal to or greater than MD, sets to N+1 the dividing ratio of the frequency dividing circuit for defining the integral frequency dividing interval; and a decoder circuit for outputting, to the phase adjusting circuit, a weighting signal for deciding, on the basis of the cumulative result, the interior division ratio for dividing the timing difference in the phase adjusting circuit.
With the PLL circuit according to the present invention, a clock having a frequency of fvco/(N+MF/MD), which is obtained by dividing a frequency fvco of the output of the voltage-controlled oscillator by the dividing ratio N+MF/MD at all times, is input to the phase comparator circuit.
In accordance with another aspect of the present invention, the phase adjusting circuit includes an interpolator comprises: a logic circuit, which receives two clocks of mutually different phases from two input terminals as first and second input signals, for outputting the result of a prescribed logic operation of the first and second input signals; a first switch element, which is connected between a first power supply and an internal node and to a control terminal whereof an output signal from said logic circuit is input, for being turned on when both the first and second input signals are at a first value to thereby form a path that charges the internal node; a plurality of series circuits, each of which comprises a second switch element turned on when the first input signal is at a second value and a third switch element turned on and off based upon the weighting signal, a plurality of series circuits being connected in parallel between the internal node and a second power supply; and a plurality of series circuits, each of which comprises a fourth switch element turned on when the second input signal is at the second value and a fifth switch element turned on and off based upon the weighting signal, a plurality of series circuits being connected in parallel between the internal node and the second power supply.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.